1. Field of the Invention
The present invention concerns an integrated circuit that implements a field programmable gate array (FPGA).
2. Description of the Prior Art
Integrated circuits (ICs) have traditionally implemented a single function, or else functions that were defined by software programming. However, in either case, the logic architecture that implemented the functionality was fixed during the design of the IC. More recently, integrated circuits have been developed whose logic architecture can be changed after manufacture. For example, Programmable Logic Devices (PLDs) and Field Programmable Gate Arrays (FPGAs) have been developed whose logic functions can be established by the user. One type of FPGA implementation is shown, for example, in U.S. Pat. No. 4,870,302. Referring to FIG. 1, a typical FPGA architecture is illustrated. The logic functions arc typically done in Programmable Function Units (PFUs) 100, 101, 102, 103, which are alternatively referred to by workers in the art as Configurable Logic Blocks (CLBs). Each PFU includes various logic circuit elements (AND gates, OR gates, NAND gates, NOR gates, flip-flops, multiplexers, registers, latches, and tristate buffers, for example ) that may be connected in a desired arrangement in order to implement desired logic and memory functions. For example, typical logic functions include combinatorial logic, adders, counters, and other data path functions. Furthermore, the connections between the PFUs may also be established as desired. Some of the means used or proposed for establishing the desired connectivity within and/or between PFUs include fuses, anti-fuses, and pass transistors controlled by program registers or electronically-erasable programmable read-only memories (EEPROMs), for example.
As illustrated in FIG. 1, the PFUs are connected together by Routing Nodes (R-nodes), being illustratively the conductors in groups 104, 105, 106 and 107. In addition, Configurable Interconnect Points (CIPs) arc used to connect two or more R-nodes together. The CIPs may be grouped as C-blocks (e.g., 108) and S-blocks (e.g., 109), whose functions arc described below. Due to their symmetric layout, FPGAs may conceptually be divided into more or less identical blocks of circuitry called Programmable Logic Cells (PLCs). For example, a given PLC (117) typically includes a single PFU (101), and the associated R-nodes and CIPs as described above. Around the periphery of the integrated circuit are programmable Input/Output cells (e.g., 111, 112), also referred to as "PIC" herein. These include Input/Output blocks (e.g., 113, 114, 115 and 116) that communicate externally to the integrated circuit via bondpads (e.g., 117, 118, 119, 120).
In the current FPGA architectures, the R-nodes are typically broken into two classes:
Access R-nodes: The input and output R-nodes used to route signals into or out of a PFU or Programmable Input/Output cell (PIG). For example, conductor groups 104 and 105 that connect to PFU 100 are referred to as the PFU Access R-nodes herein. Similarly, the input and output R-nodes used to route signals into or out of a Programmable Input/Output cell (PIC) are referred to as a PIC Access R-nodes. PA1 Inter-Block R-nodes: The R-nodes used to route from one block to another block. For example, conductor group 106 that connects C-block 108 and S-block 109, and conductor group 107 that connects S-block 109 and C-block 110.
Connections are typically made from the Access R-nodes to/from the Inter-Block R-nodes by directly connecting the two R-nodes together with a CIP (a buffer may or may not be included). These types of connections are typically grouped into a block for each PLC called a connection block (C-Block). For example, if a signal is an output of a PFU (100) it is placed on an output PFU Access R-node (e.g., in group 105) and may then be placed on a horizontal Inter-Block R-node (e.g., in group 107) by turning on a CIP (e.g., in block 110) that directly connects the two R-nodes. Similarly, if a signal is an input to a PFU it would be taken from an Inter-B lock R-node and then placed on an input PFU Access R-node by again turning on a CIP that directly connects the two R-nodes. Connections between the Inter-Block R-nodes are also made by directly connecting the two R-nodes together with a CIP (again a buffer may or may not be included). For example, if the horizontal Inter-Block R-node above is to "turn a corner" and be placed on a vertical Inter-Block R-node, this is accomplished by turning on a CIP that directly connects the two R-nodes. These types of connections are typically grouped into a block for each PLC called a switch matrix block (S-Block).
FIGS. 2(A) and 2(B) then show an example of how the connections inside the C-Block and S-Block can be implemented. In FIG. 2(A), a C-block is illustrated, wherein the vertical routing conductors 201 and 202 may be selectively connected to the horizontal routing conductor 203 by means of the CIPs 205 and 205. Similarly, the vertical routing conductors may be connected to the other horizontal conductors 204, 207, 208, 209 and 210 by the other CIPs illustrated. As shown in FIG. 2(A), each CIP is illustrated as a diamond, and typically comprises a field effect transistor having a first source/drain region connected to the vertical conductor, and a second source/drain region connected to the horizontal conductor. The gate of the transistor is controlled by a register (not shown), or other means of storing the desired connectivity information. In the case of an n-channel transistor, when the gate voltage on the transistor is high, the transistor conducts, which connects the two conductors. For purposes of illustration herein, a filled-in diamond illustrates the case of a conducting CIP. When the gate voltage is low, the transistor does not conduct. This is illustrated herein as an open diamond for the CIP. As described above, these connections may alternatively be made by fuses, anti-fuses, etc.
In FIG. 2(B ), a typical S-block 250 is illustrated. The vertical conductor 251 is selectively connected to the horizontal conductor 253 by means of transistor 257, and to the horizontal conductor 254 by means of transistor 258. Similarly, the vertical conductor 263 is selectively connected to horizontal conductors 253 and 254 by means of transistors 259 and 260, respectively. The vertical conductors 251 and 263 are selectively connected together by transistor 262, whereas the horizontal conductors 253 and 254 are selectively connected together by transistor 261. In an analogous manner, the vertical conductors 252 and 264 and the horizontal conductors 255 and 256 may be selectively connected by the other transistors shown.
The problem with the above-type of architecture is that for every pair of R-nodes that need to be connected together a CIP is needed. Since each of these CIPs consist of components of significant size, this greatly increases the size of the FPGA. Due to this size increase, FPGA architectures have tended to allow only a subset of the possible connections between multiple pairs of R-nodes. But this reduction in the number of possible connections between R-nodes makes it more difficult to route designs on a given FPGA. Therefore, it would be desirable to have an FPGA routing architecture that would allow for fewer CIPs to be used to route multiple R-nodes together. Thus the overall size of the routing architecture could be smaller.